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DATA SHEET
COMPOUND TRANSISTOR
PA104
HIGH FREQUENCY NPN TRANSISTOR ARRAY
FEATURES
* 9 GHz CONFIGURABLE TRANSISTOR BASED OR/NOR CIRCUITRY * OUTSTANDING hFE LINEARITY * TWO PACKAGE OPTIONS: PA104B: Studded ceramic package provides superior thermal dissipation PA104G: Reduced circuit size due to 14-pin plastic SOP package for surface mounting * EXCELLENT FOR ANALOG ADDITIONS & FORMATION OF 2-INPUT OR/NOR GATES
DESCRIPTION AND APPLICATIONS
The PA104 is a user-configurable, Si bipolar transistor array for formation of high speed OR/NOR gates. Its internal transistor configuration and external connection options allow the user considerable flexibility in its application. Its high gain bandwidth product (fT = 9 GHz) make it applicable for electro-optical, signal processing, cellular telephone systems, instrumentation, and high speed gigabit logic circuits.
ORDERING INFORMATION
PART NUMBER PACKAGE 14-pin ceramic package 14-pin plastic SOP (225 mil)
PA104B-E1 PA104G-E1
ABSOLUTE MAXIMUM RATINGS (TA = +25 C)
SYMBOLS VCBO* VCEO* VEBO* IC* PT PARAMETERS Collector to Base Voltage Collector to Emitter Voltage Emitter to Base Voltage Collector Current Power Dissipation PA104B PA104G Junction Temperature PA104B PA104G Storage Temperature PA104B PA104G UNITS V V V mA mW mW C C C C RATINGS 15 6 2.5 40 650 350 200 125 -55 to +200 -55 to +125
TJ
TSTG
* Absolute maximum ratings for each transistor.
Caution electro-static sensitive devices
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. P10709EJ2V0DS00 (2nd edition) Date Published October 1999 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1995, 1999
PA104
PACKAGE DIMENSIONS (UNIT: mm)
PA104B
14 PIN CERAMIC PACKAGE
0.8 TOP VIEW
0.35 6.2 1.27
5.0 MAX. 2. 7 SIDE VIEW MAX.
4.5 MIN. 0.08
2.3 MIN.
1.6
BOTTOM VIEW
1.8
3.0
PA104G
14 PIN PLASTIC SOP (225 mil)
14
8
detail of lead end
3 -3 1 10.2 0.26 1.49 7
+7
6.55 0.2 4.38 0.1 1.1 0.16
0.6 0.2 1.27 0.40 +0.10 -0.05 0.1 0.1 1.59 +0.21 -0.20 NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 0.10 M 1.42 MAX 0.15 -0.05
+0.10
0.10
See connection diagram for description of leads.
2
Data Sheet P10709EJ2V0DS00
PA104
ELECTRICAL CHARACTERISTICS (Unless otherwise specified TA = +25 C PA104B, PA104G common)
SYMBOLS ICBO IEBO hFE CCB CEB CCS fT PARAMETERS AND CONDITIONS Collector Cutoff Current at VCB = 5 V, IE = 0 (Q1 thru Q6) Emitter Cutoff Current at VEB = 1 V, IC = 0 (Q4 thru Q6) Direct Current Amplification at VCE = 3 V, IC = 5 mA (Q4 and Q6) Collector to Base Capacitance at VCB = 3 V, f = 1 MHz (Q3, Q5, Q6) Emitter to Base Capacitance at VEB = 0, f = 1 MHz (Q4 thru Q6) Collector/Substrate Capacitance, VCS = 3 V, f = 1 MHz (Q3, Q5, Q6) Gain Bandwidth Product* at VCE = 3 V, IC = 10 mA pF pF pF GHz UNITS MIN. TYP. MAX. 1.0 1.0 40 100 0.9 1.4 1.4 9.0 250 1.8 2.8 2.8
A A
* Measured by installing a single transistor in a Micro-X package: the value shown is a reference value.
CONNECTION DIAGRAM (Top View)
PA104B
14 13 12 11 10 9 8
Q6 Q5 Q1 SUB Q4 Q2 Q3
1
2
3
4
5
6
7
PA104G
14 13 12 11 10 9 8
Q5 Q1 Q2 Q3
Q6
Q4
1
2
3
4
5
6
7
Note: Substrate should be connected to the lowest voltage point in order to prevent latch-up.
Data Sheet P10709EJ2V0DS00
3
PA104
TYPICAL PERFORMANCE CHARACTERISTICS (TA = +25 C)
COLLECTOR CURRENT vs. COLLECTOR TO EMITTER VOLTAGE 10 100 Collector Current, IC (mA) 8 80 60 40 IB = 20 A Collector Current, IC (mA) 200 100 50 20 10 5 2 1 0.5 VCE = 3 V 0 0 1 2 3 4 5 Collector to Emitter Voltage, VCE (V) 0.1 0 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 Base to Emitter Voltage, VBE (V) COLLECTOR CURRENT vs. BASE TO EMITTER VOLTAGE
6
4
2
DC CURRENT GAIN vs. COLLECTOR CURRENT Gain Bandwidth Product, fT (GHz) 1000 12
GAIN BANDWIDTH PRODUCT vs. COLLECTOR CURRENT
DC Current Gain, hFE
10
VCE = 5 V
200 VCE = 3 V 100 50 20 10 0.5 1 2 5 10 20 Collector Current, IC (mA) 50
8 3V 6 1V 4
1
2 5 10 20 Collector Current, IC (mA)
50
GAIN AND NOISE FIGURE OF INDIVIDUAL TRANSISTOR 20 VCC = 3 V f = 1 GHz GAIN Gain (dB) 6 10 4 Noise Figure, NF (dB) 8
NF 0
2
1
2
5 10 20 50 100 Collector Current, IC (mA)
0
4
Data Sheet P10709EJ2V0DS00
PA104
TYPICAL APPLICATION
A B A+B
OR
A
B VCC (+2 V) 100 115 300
OR 50 50 K 50 K 47 100 1.5 K 2.8 K VEE (-3.2 V) VBB (-1.6 V)
+1.1 V IN 50 % t++ OUT (OR) 50 % 50 % t-- 50 % tf 90 % 10 % t++ = 500 psec. t-- = 250 psec. tR +0.3 V
tf = 500 psec. tR = 750 psec.
The application circuits and their parameters are for references only and are not intended for use in actual design-in's.
Data Sheet P10709EJ2V0DS00
5
PA104
NOTES ON CORRECT USE
(1) Observe precautions for handling because of electro-static sensitive devices. (2) Form a ground pattern as wide as possible to maintain the minimum ground impedance (to prevent undesired oscillation). (3) Design circuits connected Sub pin to the lowest voltage to prevent latch-up. (4) Design circuits as each pin voltage difference within 15 V maximum.
RECOMMENDED SOLDERING CONDITIONS
This product should be soldered in the following recommended conditions. Other soldering methods and conditions than the recommended conditions are to be consulted with our sales representatives.
PA104G
Soldering process Infrared ray reflow Soldering conditions Package peak temperature: 235 C, Hour: within 30 s. (more than 210 C), Time: 2 times, Limited days: no.Note Package peak temperature: 215 C, Hour: within 40 s. (more than 200 C), Time: 2 times, Limited days: no.Note Soldering tub temperature: less than 260 C, Hour: within 10 s. Time: 1 time, Limited days: no.Note Pin area temperature: less than 300 C, Hour: within 3 s./pin Limited days: no.Note Recommended condition symbol IR35-00-2
VPS
VP15-00-2
Wave soldering
WS60-00-1
Pin part heating
PA104B
Soldering process Infrared ray reflow Soldering conditions Peak package's surface temperature: 230 C or below, Reflow time: 10 seconds or below (210 C or higher), Number of reflow process: 1, Exposure limit*: None Terminal temperature: 260 C or below, Flow time: 10 seconds or below, Exposure limit*: None Symbol
Partial heating method
Note It is the storage days after opening a dry pack, the storage conditions are 25 C, less than 65 % RH. Caution The combined use of soldering method is to be avoided (However, except the pin area heating method). For details of recommended soldering conditions for surface mounting, refer to information document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E).
6
Data Sheet P10709EJ2V0DS00
PA104
[MEMO]
Data Sheet P10709EJ2V0DS00
7
PA104
NESAT (NEC Silicon Advanced Technology) is a trademark of NEC Corporation.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98.8

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